PowerVR Rogue USC

Executing multiple instructions in a single cycle

Shader performance on PowerVR Rogue architecture GPUs depends on the number of cycles it takes to execute a shader. Depending on the configuration, the PowerVR Rogue architecture delivers a variety of options for executing multiple instructions in the USC ALU pipeline within a single cycle. Some of these instructions are explained in more detail further along in this guide.

For example, it is possible to execute all of the following in one cycle:

  • Two F16 SOP instructions
  • The F32 <-> F16 conversions
  • The MOV/OUTPUT/PACK instruction.

As can all of these in one cycle:

  • An FP32 MAD
  • An FP32/INT32 MAD/UNPACK instruction
  • A test (conditional) instruction
  • The MOV/OUTPUT/PACK instruction.

If there is bitwise work to be done, these can all be executed in one cycle too:

  • A bitwise SHIFT/COUNT
  • A bitwise logical operation
  • A bitwise SHIFT
  • A test (conditional) instruction
  • The MOV/OUTPUT/PACK instructions.

Other possibilities for execution in one cycle include:

  • A single complex operation (such as RCP) and a MOV/OUTPUT/PACK instruction
  • An interpolate/sample instruction plus the usual MOV/OUTPUT/PACK instruction.

As shown in the diagram below, it is best to use all stages in one route in the pipeline below to make full use of the ALU. Therefore, GLSL instructions should be arranged in that way.