Hardware Terms: Quick Reference

A reference of common terms found in PVRTune

The table below shows a list of common hardware terms to help interpret the statistics displayed in PVRTune. For a more detailed interpretation, use the help feature in PVRTune, as the statistics will change depending on the hardware.

Note: Refer to the “PowerVR Hardware Architecture Guide” for a more detailed understanding of the PowerVR hardware architecture.
Table 1. Quick reference of hardware terms
Term Description
Tiler The Tiler is responsible for processing the vertices and tiling. This includes transforming vertices, culling, clipping, and storing the data. The timing data contains the Tile Accelerator (TA) and Vertex Shader processing operations.
Renderer The Renderer is responsible for processing the fragments within a given tile. The timing data contains all the ISP, TSP, and fragment shader processing operations.
TA Tile Accelerator. See Tiler.
TSP The Texture and Shading Processor (TSP) performs interpolation and schedules tasks for the shader processor and texture data pre-fetches.
ISP The Image Synthesis Processor (ISP) is responsible for per-tile Hidden Surface Removal (HSR) to ensure that the fragments processed by the TSP are only those that will affect the rendered image.
Shader The PowerVR shader processor is a flexible, multi-threaded processor capable of executing vertex, fragment, graphics core instructions, and issuing memory access operations such as texture fetches.
Compute Series6 only: The Compute Core is dedicated to compute tasks issued via the Compute Data Master (CDM). Compute timing data includes the programmable arithmetic handled by the shader processor.