Structure of ISR assembly code

To aid programming, and support instruction co-issue, program instruction groups are used.

Instruction co-issue is where multiple instructions are issued, in a single clock cycle, to run in the multiple phases of the Unified Shading Cluster (USC) Pipeline Datapath (USCPD).

The Arithmetic Logic Unit (ALU) pipeline allows up to 6 instructions (1 per phase + backend) to be issued within a clock. These instructions are presented to the assembler as a "group" of instructions.

The general layout of an instruction group can be seen below:

[n] : [if (cond)] # n is group number (if is optional)
 [Op 0] # First op 
 [Op 1] # Second op (optional)
 ..
 [Op N] # Nth operation (optional)
Note: Some of the commands are removed in the interest of clarity. However, the main instructions are still there, so it is sufficient to optimise code based on the disassembly output.