Types of Registers

A list of the different types of registers available within PowerVR GPUs

Temporary

Code: Rn[IDXi, D]

Access: Read/Write

Max Available: 248 (n)

Description: Temporary Registers are used for general purpose calculation and are uninitialised.

Temporary Registers are allocated from the Unified Store and may be indexed

(D is dimension can be [1, 2, 4, 8, 16], default value is 1 if omitted)

Vertex Input

Code: Vin[IDXi, D]

Access: Read/Write

Max Available: 248 (n)

Description: Vertex Input Registers behave similarly to Temporary Registers except they contain pre-initialised inputs to each instance.

Vertex Input Registers are allocated from the Unified Store and may be indexed.

Table 1. Example:
void main()
{
    gl_Position = inVertex;
}
0    : mov ft0, vi3
       mov ft0.e0.e1.e2.e3, ft0
       uvsw.write ft0, 3;

Coefficient Registers (Normal/Alternate set)

Code: CFn[IDXi, D], CFAn[IDXi, D]

Access: Read/Write

Max Available: Architecture Dependent (n)

Description: Coefficient Registers (and the alternate set) contain pre-initialised inputs shared between multiple instances of the same thread. They are normally read-only but may be written to if multiple instances ensure they do not clash by writing the same registers – the USC does not perform hazard checking for this.

Coefficient Registers are allocated from the Common Store and may be indexed.

They are used for interpolating vertex shader outputs between vertices.

Table 2. Example:
void main()
{
    fragColor = vec4(textureCoordinate, 0.0, 1.);
}
0    : fitr.pixel r0, drc0, cf4, cf0, 2;
                  

Shared Registers

Code: SHn[IDXi, D]

Access: Read/Write

Max Available: 4096 (n)

Description: Shared Registers contain pre-initialised inputs shared by an entire thread. They are normally read-only but may be written to if multiple instances ensure they do not clash by writing the same registers – the USC does not perform hazard checking for this.

Shared Registers are allocated from the Common Store and may be indexed.

Table 3. Example:
uniform vec4 t;
                    
void main()
{
    fragColor = t;
}
0    : mov ft0, sh0
       mov r0.e0.e1.e2.e3, ft0
       mov r1, sh1;
                  

Index Registers

Code: IDXi

Access: Read/Write

Max Available: 2 (i)

Description: The Index Registers are used to index other register banks and are uninitialised.

Pixel Output Registers

Code: On[IDXi, D]

Access: Read/Write

Max Available: Architecture Dependent (n)

Description: Pixel Output Registers are used by each instance of a pixel shader to output data to the PBE module.

If there are tiles per USC Pixel Output Registers are allocated from the Partition Store and may be indexed.

If this is not the case, Pixel Output Registers are allocated from the Common Store and may be indexed.

Special Constant

Code: SCn / SRn

Access: SC: read-only. SR: some are Read/Write

Max Available: 240 (n)

Description: Special Constants contain fixed values that may be useful to an instance. These are always present for each thread (they do not have to be allocated from either store) and are described in the tables below.

The Special Constants logical memory space, SC, contains "Special Constants". These are values which are truly constant for a particular instance of a program.

To help with using shorter encodings the special constants are interleaved, so the most commonly used are available with 6-bit offsets. They are interleaved 32 values each.

8 offset registers are provided, registers 36-43.

Note: Although offsets 0 to 7 are provided for Internal Registers, the actual number of Internal Registers and offsets depends on the configuration and will not exceed 8.
Note: Although offsets 0 to 7 are provided for Slot Registers, the actual number of Slot Registers and offsets depends on the configuration and will not exceed 8. The total number of Slot Registers and Internal Registers will not exceed 8.

You can find a list of these registers in the appendix.

Table 4. Example:
void main()
{
	fragColor = vec4(1.0);
}
0    : mov ft0, c64 #c64 = 1.0
       mov r0.e0.e1.e2.e3, ft0
       mov r1, c64;

Vertex Output Registers

Code: Von

Access: Write-only

Max Available: 256 (n)

Description: Vertex Output Registers are used by each instance to output data to the UVS module. They exist outside of the USC and as such are write-only using the UVSW instruction.

Vertex Output Registers may be indexed. They may only be written using the UVSW instruction.

Dynamic Constant Registers (optional)

Code: DCn [IDXi, D]

Access: Read-only

Max Available: 16384 (n)

Description: Dynamic Constant Registers are large arrays of constants that exist in main memory to which the USC manages windows of 16 read only registers per instance.

Dynamic Constant Registers must be indexed.

Internal Registers (optional)

Code: In

Access: Read/Write

Max Available: Architecture Dependent (n)

Description: Internal Registers used for general purpose calculation and are uninitialised.

They are similar to Temporary Registers but are not allocated from the Unified Store, instead there is a dedicated set per instance. As such they cannot be used for DMA or FITR operations.

Internal Registers may not be indexed.

The number of Internal Registers available is dependent on the configuration of Rogue and may range from not being available at all to 8 registers.

Slot Registers (optional)

Code: Sln

Access: Read/Write

Max Available: Architecture Dependent (n)

Description: Slot registers are used for general purpose calculations that are not dependent on data, such as loop counters. They are similar to a shared registers allocation that is not initialised in that only one instance will write into this register per instruction, however the Slot Registers are not visible to other threads.

The number of Slot Registers available is dependent on the configuration of Rogue and may range from not being available at all to 8 registers.