General Architecture Information

The Unified Shading Cluster (USC) assembly code described in this Instruction Set Reference (ISR) drives the USC component(s) of the PowerVR architecture.

The Unified Shading Cluster (USC) assembly code described in this Instruction Set Reference (ISR) drives the USC component(s) of the PowerVR architecture.

The information in this document enables developers to write shaders that use the hardware more efficiently.

Even though most of the information in this document applies to the PowerVR Series 6XT architecture, parts that may not be applicable on all PowerVR architectures have been labelled as optional.

Refer to the main PowerVR ISR document (NDA required) for precise information regarding feature availability.

Below is the hierarchical description of a USC with the important parts in bold.

A USC comprises:

  • USC Common Store (CS or USCCS)
  • USC Pipeline Datapaths (USCPDs)
  • Iterators
  • DMA Output
  • F64 ALU-Pipeline datapath (optional)

Each USCPD comprises:

  • Unified Store (US)
  • Bypass FIFO
  • One ALU Pipeline

The Arithmetic Logic Unit (ALU) Pipeline in each USCPD comprises:

  • ALU Instances
  • Sideband/Control Bypass Pipeline
  • Texture Address Unit (TAU) (optional)

Each ALU Instance contains a set of ALUs (see 'ALU Partitioning') and comprises:

  • ALU Source unit – selects sources, and swizzles
  • ALU Phase 0 – arithmetic operations for phase 0
  • ALU Phase 1 – arithmetic operations for phase 1
  • ALU Phase 2 – arithmetic operations for phase 2
  • ALU Move – final multiplexing of results
  • F16 ALU-phases (optional)

The pipeline operates in Single Instruction Multiple Data (SIMD) mode across multiple parallel data instances that are processed at a rate of one scalar component per clock, in other words, it is not a vector pipeline.