Rogue Architecture Glossary

Glossary of the acronyms used in this document

Term

Meaning

CDM

Compute Data Master. Generates USC compute tasks.

CGS

Coarse Grain Scheduler. The top-level scheduler and resource manager for the USC.

CMU

Core Management Unit. Responsible for handling graphics core events and interrupts.

FGS

Fine Grain Scheduler. Small granularity scheduler for the USC.

HSR

Hidden Surface Removal.

ISP

Image Synthesis Processor. The HSR, depth and stencil processing module.

META

32-bit multithreaded microprocessor developed by Imagination Technologies.

PB

Parameter Buffer. Area in memory where vertex and tile data are stored.

PBE

Pixel Back End. The module responsible for final pixel processing and system memory write operations

PDM

Pixel Data Master. Pixel rasterization block. Includes the ISP and TSPF.

SIMD

Single Instruction Multiple Data. Hardware architecture where multiple processing elements perform the same operation on multiple data points simultaneously.

TA

Tile Accelerator. Main unit to generate the data for the Parameter Buffer.

TPU

Texture Processing Unit. Responsible for fetching and filtering texels.

TSPF

Texture and Shading Parameter Fetch. Calculates the required plane equations and issues texture pre-fetch operations.

USC

Universal Shader Cluster. The main arithmetic processing block.

[USC] lane

Arithmetic processing unit of a USC.

[USC] thread

An execution of an item of work by a USC lane.

USCA

Universal Shader Cluster Array. A USCA consists of one of more USCPs.

USCP

Universal Shader Cluster Pair. Two USC processing units paired with a TPU.

VCE

Vertex Compression Engine. Compresses the Parameter Buffer data.

VDM

Vertex Data Master. Generates USC vertex tasks.

UVS

Unified Vertex Store. UVS is a block of memory used as temporary storage by the Vertex phase.