Example Chip Configurations

A reference for the chip configurations of different PowerVR architecture families

9XM

8XE

6XT

7XT

Chip

MediaTek P80

MediaTekClark

MediaTek MT8173

MediaTek X30

Product name

'GM9445' 'GE8300'

'GX6250'

MSAA max samples

4

4

8

8

2xMSAA full-rate

Yes

Address width

36 bits

32 bits

40 bits

40 bits

Bus Count

2

1

2

2

Bus Width

128

128

128

128

CDM task killing

Yes

Yes

Clusters

2

1

2

4

Compute overlap

Yes

No

Partial (without barriers only)

Yes

Draw Indirect (Native)

Yes

Dynamic constants

Yes

FBCDC algorithm

v2

v2

FBCDC architecture

v2

v3

Fast clears

Yes

Yes

Yes

Yes

Flushable compute kernels

Yes

Framebuffer compression

Yes

Yes

Yes

Framebuffer compressor

v3

v1

v3

Framebuffer decompressor

v1

v3

GPU virtualisation

Yes

Yes

Yes

Geometry shaders

Yes

Yes

Yes

Yes

ISP depth buffers

6

4

4

16

ISP extended depth formats (D16/D24)

Yes

Yes

Yes

ISP fast tag sorter

Yes

Yes

ISP maximum tiles in flight

6

3

4

2

ISP punchthrough banks

8

16

ISP resolve depth for MSAA

Yes

ISP samples per pixel

1

1

2

2

ISP tag buffers

5

6

MCU can only flush to the SLC

Yes

MCU size

Unconfigured

Unconfigured

24

MMU pagetable TLB banks

2

MMU pagetable TLB size

64 entries

New 2D datamaster (TDM)

Yes

Number of rasterization pipelines

2

1

1

1

Number of shader pipelines

2

1

1

1

Number of user clip planes

8

8

8

8

Number of virtualised OSes

8

8

8

Object-level LLS in VDM

Yes

Output Registers

8 (256-bit PLS)

8 (256-bit PLS)

8 (256-bit PLS)

PBE2 in XE core

Yes

Yes

Parallel stream out

Yes

Parameter buffer compression

Yes

Yes

SLC atomics

Yes

SLC banks

2

4

SLC cacheline size

512 bits

512 bits

SLC external tag IDs

128

128

64

192

SLC size

128 KiB

64 KiB

128 KiB

512 KiB

Series 8XE top-level infrastructure

Yes

Small MMU

Yes

Yes

Small PDS

Yes

Small PPP

Yes

Small TE

Yes

Small clipper

Yes

Yes

Small parameter manager

Yes

Stream out streams

4

TE TPC cachelines

16

TE pipelines

1

TE tiles in flight

48

TPU ASTC

Yes

Yes

Yes

Yes

TPU ASTC HDR

Yes

Yes

TPU Anisotropic filtering

Yes

Yes

Yes

Yes

TPU BC1 to BC5 support

Yes

Yes

TPU Bicubic filtering

Yes

Yes

TPU Depth compare

Yes

TPU MADD L0 size

16 entries

16 entries

8 entries

8 entries

TPU parallel instances

4

4

4

4

Tessellation

Yes

Tile IDs

32

16

10

6

Tile height

16

16

32

32

Tile per USC

Yes

Tile size

16x16

16x16

32x32

32x32

Tile width

16

16

32

32

Total bus width

128

128

256

256

Triangle merging in the PDS

Yes

Yes

Yes

Triangle merging in the PDS (always)

Yes

Yes

USC 8 and 16-bit vector ALU

Yes

USC ALU performance counters

Yes

USC Co-issue with complex ALU

Yes

Yes

USC Common Store Depth

896

1280

USC Common Store max allocation

4096 dwords

4096 dwords

4096 dwords

4096 dwords

USC Common Store size

15360 dwords

USC Common Store split partitioning

Yes

Yes

Yes

USC Common Store split point

832

832

USC F16 SOP

Yes

Yes

Yes

Yes

USC F16 SOP U8 blending

Yes

Yes

Yes

Yes

USC F16 SOP extended use

Yes

Yes

Yes

Yes

USC F16 SOP multiply-add

Yes

Yes

Yes

Yes

USC F16 support in complex ALU

Yes

Yes

USC F32 serial FMA

Yes

Yes

USC ITRSMP

Yes

Yes

Yes

Yes

USC ITRSMP + DITR

Yes

Yes

Yes

USC Instructions larger than 26 bytes

Yes

Yes

Yes

USC Internal Registers

2

4

4

USC Iterators

16

16

8

8

USC Number of slots

64

32

38

USC Number of tasks

156

104

56

72

USC Unified Store depth

208

256

256

USC age-aware scheduling

Yes

USC direct DMA ops

Yes

USC gamma expansion/compression

Yes

Yes

USC half instances

USC improved barrier performance

Yes

USC index register width

12 bits

12 bits

12 bits

14 bits

USC index registers

2

2

2

4

USC out-of-order dependencies

Yes

USC packing rounds to zero

Yes

Yes

Yes

Yes

USC parallel instances

16

8

16

16

USC partition store size

16384 dwords

USC per-cluster mutex

Yes

Yes

USC render target ID support

Yes

Yes

Yes

USC slot registers

0

0

0

4

USC workgroup ID register

Yes

UVB size

64 KiB

UVS PBA entries

640

320

320

320

UVS banks

8

4

8

8

UVS vertex entries

576

288

288

288

VCE pipelines

1

Virtual address space

40 bits

40 bits

40 bits

40 bits

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