PowerVR Rogue Family Architecture

A high-level overview of the different elements which make up the Rogue architecture

The core of the Rogue family is the Unified Shading Cluster Array (USCA), illustrated as the central area in the image below. The USCA contains Unified Shading Cluster Pairs (USCP), comprised of a shared Texture Processing Unit and two Unified Shading Clusters (USCs).

USCs are responsible for all programmable computation performed by the graphics core, for example, running vertex, fragment and compute shaders. PowerVR technology is a unified architecture, whereby all types of shaders run on the same processing block (the USC).

The Core Management Unit (CMU) handles the submission of tasks from the host graphics driver to the Data Masters (DM). There are Data Masters for each type of task that can be run on the USC units, namely: Vertex, Pixel and Compute Data Masters. The Data Masters are responsible for generating Coarse Grain Scheduler (CGS) tasks.

The CGS , also known as the PDS, manages the submission of tasks and allocation of resources for the USC units. Each of these clusters has a Fine Grain Scheduler (FGS), which is responsible for managing the tasks scheduled to run on the USC. The FGS schedules out tasks when there are data dependencies (e.g. texture fetching) and schedules in other queued tasks, enabling data fetch latency to be hidden.

The Tiling Accelerator (TA) processes vertex work output by the USC – performing tile binning. The Pixel Back End (PBE) processes pixel work output by the USC, collating and writing out rasterized tiles which the render comprises. The Texture Load Accelerator (TLA) is a piece of dedicated hardware to perform texture upload and 2D operations.