Introduction to the Rogue Architecture Guide

This document provides programmers with in-depth information about the PowerVR Rogue hardware family architecture

The purpose of this document is to provide programmers with in-depth information about the PowerVR Rogue hardware family architecture.

PowerVR is the name of Imagination Technologies graphics hardware IP family. All generations are based on our patented “Tile Based Deferred Rendering” (TBDR) architecture. The core design principle of the TBDR architecture is to keep the system memory bandwidth requirements of the graphics hardware to a bare minimum, processing and rendering only the elements that contribute to a scene.

This document assumes some basic knowledge of PowerVR TBDR architecture. For a more general overview of the PowerVR hardware architecture, please refer to the PowerVR Hardware Architecture Overview for Developers.

This document starts with an overview of the schedulers followed by a detailed description of the main processing blocks. After these two common components, we will then follow the data path inside the hardware, starting with the vertex processing, tile batching and the Parameter Buffer. This is followed by a description of the pixel processing phase and the Pixel Backend. The document finalises with an overview of the texture acceleration units and memory system.