A description of relevant graphical terms

Term Meaning
ALU Arithmetic Logic Unit. Responsible for processing shader instructions.
Early-Z An umbrella term for a collection of optimisations commonly used by graphics cores. Early-Z techniques reduce overdraw by performing depth tests early in the graphics pipeline.
Firmware A dedicated program running on the graphics core that handles hardware events.

For example: a tile processing operation completing.
Fragment The data necessary to calculate a pixel colour. Multiple fragments may contribute to the colour of a pixel.

For example: when a transparent object is drawn in front of an opaque object.
Graphics pipeline The sequence of processing stages within a graphics core that must be executed to render an image.
HSR Hidden Surface Removal.
IMR Immediate Mode Renderer.
ISP Image Synthesis Processor.
Overdraw The term “overdraw” refers to wastefully colouring pixels that do not contribute to the final image colour.
SIMD Single Instruction, Multiple Data. Concurrent execution of a single instruction across multiple ALUs, where each ALU has unique input and output.
Scalar [shader architecture] A shader architecture in which an ALU processes a single value at a time.
Pixel The smallest addressable area of a frame buffer.
Rasterization The process of determining which pixels a given primitive touches.
Render The process of converting application-submitted data into coloured pixels that can be stored in the frame buffer.
Renderer The tile processing stage of a TBDR pipeline. This includes rasterization and fragment shading.
TA Tile Accelerator.
TBR Tile Based Renderer.
TBDR Tile Based Deferred Renderer.
Tile A rectangular group of pixels. In TBR and TBDR architectures, the frame buffer is broken into many tiles. The tile size of each PowerVR graphics core is decided during hardware design, typically 32x32 pixels.
Tiler The vertex shading, clipping, projection, culling, and tiling stages of a TBDR pipeline.
TSP Texture and Shading Processor.
Vector [shader architecture] A shader architecture in which an ALU processes multiple values simultaneously. Vector architectures commonly have a width of 4, allowing the ALU to calculate values for the ‘x’, ‘y’, ‘z’ and ‘w’ components of a vector data type.