Hardware Terms: Quick Reference

The table below shows a list of common hardware terms to help interpret the statistics displayed in PVRTune. For a more detailed interpretation, use the help feature in PVRTune, as the statistics will change depending on the hardware.

Note: Refer to the PowerVR Hardware Architecture Guide for a more detailed understanding of the PowerVR hardware architecture.


Term	Description
Tiler	The Tiler is responsible for processing the vertices and tiling. This includes transforming vertices, culling, clipping, and storing the data. The timing data contains the Tile Accelerator (TA) and Vertex Shader processing operations.
Renderer	The Renderer is responsible for processing the fragments within a given tile. The timing data contains all the ISP, TSP, USC fragment and PBE processing.
TA	Tile Accelerator. See Tiler.
TPU	The Texture Processing Unit (TPU) performs texture sampling and filtering operations such as bilinear, trilinear, and anisotropic.
ISP	The Image Synthesis Processor (ISP) is responsible for per-tile Hidden Surface Removal (HSR) to ensure that the fragments processed by the TSP are only those that will affect the rendered image.
USC	The Unified Shading Cluster (USC) executes all types of programmable shaders including vertex, fragment, and compute.
CDM	The Compute Data Master (CDM) is responsible for scheduling all compute workloads. The timing data includes all USC Compute processing.
PBE	The Pixel Back End (PBE) is primarily responsible for writing out completed work to memory. The PBE also carries out common raster operations, such as dithering, format conversion, rotation, twiddling, and downscaling (resolving MSAA).