PowerVR Volcanic USC

The computing power offered by PowerVR Volcanic cores depends on the configuration of the core. Below some orientative values (based values for BXM-8-256) are given for developers to understand the virtues and limitations of this cores:

Two instructions per cycle: - F16 MAD or SOP operations. - Instruction decoding.

One instruction per cycle: - F32 MAD or SOP operations. - Integer & Bitwise calculations: Since they are done on a secondary ALU pipeline, computing power of 50% to 25% when compared with F32 computing power.

One instruction per 4 cycles: - F32 transcendental / complex operations (sin(), cos(), exp()): Up to 4 cycles per operation at maximum USC utilization, done on a separate ALU pipeline, with a computing power of 50% to 25% when compared with F32 computing power. - MOV operations between different local memory stores: Taking up to 8 cycles for format conversion. - Conditional execution evaluations for flow control: Up to 4 cycles depending on USC utilization.

For those operations involving texture and pixel performance, 16 cycles are needed per texel / pixel using 32-bit texture formats.